EP910LI-35 vs EP910LI-35Y Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910LI-35 sa pamamagitan ng Altera at EP910LI-35Y sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910LI-35 | EP910LI-35Y |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | NRND |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Device Series | EP910 | — |
| Usable Gates | 900 | 450 |
| Macrocells | 24 | 24 |
| Maximum User I/O Pins | 38 | — |
| Propagation Delay (t_PD) | 35 ns | — |
| Maximum Counter Frequency (f_CNT) | 76.9 MHz | — |
| Volte ng Pagbibigay | 5 V (4.75 V to 5.25 V) | — |
| Temperature na Operasyon | -40 °C to +85 °C (Industrial) | — |
| Packhaging | 44-pin PLCC (J-lead) | PLCC-44 (J-lead) |
| Process Technology | CMOS EPROM | — |
| Programming Technology | EPROM (UV-erasable) | — |
| Erase/Program Cycles | ≥100 | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Lead Pitch | 1.27 mm | — |
| Propagation Delay (tpd) | — | 35 ns |
| Maximum Frequency (fmax) | — | [DATA_NEEDED: maximum toggle frequency in MHz] |
| Supply Voltage (VCC) | — | 5 V |
| Process Option | — | L (low-power CMOS) |
| Temperature Grade | — | Industrial (-40 °C to +85 °C) |
| Lead Finish | — | Lead-free (Y suffix, RoHS-compliant) |
| I/O Pins | — | 24 |
| Dedicated Inputs | — | 36 |
| Technology | — | CMOS EPROM/UV-erasable |
| Tindminan RoHS | — | Compliant (Y suffix) |