EP910LI-35Y vs EP910LC-30 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910LI-35Y sa pamamagitan ng Intel at EP910LC-30 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910LI-35Y | EP910LC-30 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | Altera Classic EPLD | — |
| Usable Gates | 450 | — |
| Macrocells | 24 | — |
| Propagation Delay (tpd) | 35 ns | — |
| Maximum Frequency (fmax) | [DATA_NEEDED: maximum toggle frequency in MHz] | — |
| Supply Voltage (VCC) | 5 V | 5 V (nominal, TTL) |
| Process Option | L (low-power CMOS) | — |
| Temperature Grade | Industrial (-40 °C to +85 °C) | — |
| Packhaging | PLCC-44 (J-lead) | — |
| Uri ng Pagpapasok | Surface Mount | — |
| Lead Finish | Lead-free (Y suffix, RoHS-compliant) | — |
| I/O Pins | 24 | — |
| Dedicated Inputs | 36 | — |
| Technology | CMOS EPROM/UV-erasable | — |
| Tindminan RoHS | Compliant (Y suffix) | [DATA_NEEDED: RoHS status] |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Macrocell Count | — | 24 |
| Propagation Delay (tPD) | — | 30 ns (max) |
| Maximum Toggle Frequency | — | 62 MHz |
| Process Technology | — | CMOS (EPROM-based) |
| Package Type | — | PDIP-40 (Plastic DIP, through-hole) |
| Operating Temperature Grade | — | Commercial (0C to +70C) |
| I/O Pin Count | — | 24 |
| Dedicated Input Pins | — | 36 (including I/O) |
| Product Terms per Macrocell | — | Up to 16 |
| Programming Technology | — | UV-erasable EPROM cell |
| Development Tool | — | Altera MAX+PLUS II |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |