EP910LI-40 vs EP910LI-35 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910LI-40 sa pamamagitan ng Altera at EP910LI-35 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910LI-40 | EP910LI-35 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Manufacturer | Altera (now Intel PSG) | — |
| Product Family | Classic EPLD - EP910 series | — |
| Device Type | Erasable Programmable Logic Device (EPLD) | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | — |
| I/O Pins | 24 bidirectional | — |
| Maximum Logic Inputs | 36 | — |
| Product Terms | 240 | — |
| Propagation Delay (tPD) | 40 ns | — |
| Technology | Low-power CMOS (L-suffix) | — |
| Temperature na Operasyon | -40C to +85C (industrial, I-suffix) | -40 °C to +85 °C (Industrial) |
| Packhaging | PLCC-44 (J-lead, windowed ceramic) | 44-pin PLCC (J-lead) |
| Uri ng Pagpapasok | Surface Mount (socket-compatible) | Surface Mount |
| Programmability | UV-erasable, JEDEC-standard algorithm | — |
| Tindminan RoHS | Non-compliant (windowed ceramic PLCC, legacy) | — |
| Lifecycle | Obsolete - replaced by MAX 7000 / MAX II CPLD family | — |
| Family | — | Altera Classic EPLD |
| Device Series | — | EP910 |
| Usable Gates | — | 900 |
| Maximum User I/O Pins | — | 38 |
| Propagation Delay (t_PD) | — | 35 ns |
| Maximum Counter Frequency (f_CNT) | — | 76.9 MHz |
| Volte ng Pagbibigay | — | 5 V (4.75 V to 5.25 V) |
| Process Technology | — | CMOS EPROM |
| Programming Technology | — | EPROM (UV-erasable) |
| Erase/Program Cycles | — | ≥100 |
| Lead Pitch | — | 1.27 mm |