EP910PI-25 vs EP910PI-20T Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910PI-25 sa pamamagitan ng Intel at EP910PI-20T sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910PI-25 | EP910PI-20T |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Device | EP910 | EP910 |
| Macrocells | 24 | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 24 | — |
| Pin-to-Pin Propagation Delay (tPD) | 25 ns | — |
| Maximum Clock Frequency (fMAX) | 40 MHz | — |
| Supply Voltage (VCC) | 5 V nominal | — |
| Process Technology | 5 V CMOS (EPROM-based) | — |
| Packhaging | PDIP-40 (Plastic DIP) | PDIP-40 (PI) |
| Bilang ng Pin | 40 | — |
| Uri ng Pagpapasok | Through-Hole | Through-Hole (DIP) |
| Temperature na Operasyon | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| Programmability | UV-erasable (windowed) / one-time-programmable | — |
| Tindminan RoHS | Non-compliant (PDIP package) | unknown |
| Number of Macrocells | — | 24 |
| Number of Usable Gates | — | [DATA_NEEDED: usable gate count] |
| Propagation Delay (tpd) | — | 20 ns |
| Maximum Toggle Frequency | — | 62.5 MHz |
| Number of Dedicated Inputs | — | 12 |
| Number of I/O Pins | — | 20 |
| Bilang ng Pins | — | 40 |
| Technology | — | CMOS EPROM (UV-erasable) |
| Programming | — | Standard EPROM programmer, JEDEC map |
| Katayuan ng Lifecycle | — | Not Recommended for New Designs (NRND) |