EP910PI-25T vs EP910PI-20T Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910PI-25T sa pamamagitan ng Altera at EP910PI-20T sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910PI-25T | EP910PI-20T |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | Altera Classic EPLD Family | Altera Classic EPLD |
| Macrocells | 24 | — |
| Equivalent Gates | 900 (SSI/MSI equivalent) | — |
| Maximum Inputs | 36 | — |
| Maximum Outputs | 24 | — |
| Propagation Delay (tpd) | 25 ns | 20 ns |
| Supply Voltage (VCC) | 5 V | — |
| Technology | CMOS, UV-erasable EPROM | CMOS EPROM (UV-erasable) |
| Packhaging | 40-pin PDIP (600-mil) | PDIP-40 (PI) |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Programming | UV-erasable | Standard EPROM programmer, JEDEC map |
| Uri ng Pagpapasok | Through-Hole (DIP) | Through-Hole (DIP) |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | unknown |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Static Power | <100 mW (typical CMOS) | — |
| Device | — | EP910 |
| Number of Macrocells | — | 24 |
| Number of Usable Gates | — | [DATA_NEEDED: usable gate count] |
| Maximum Toggle Frequency | — | 62.5 MHz |
| Number of Dedicated Inputs | — | 12 |
| Number of I/O Pins | — | 20 |
| Bilang ng Pins | — | 40 |
| Katayuan ng Lifecycle | — | Not Recommended for New Designs (NRND) |