EPC144ICC20 vs EPC1213LI20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPC144ICC20 sa pamamagitan ng Altera at EPC1213LI20 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPC144ICC20 | EPC1213LI20 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | Memory ICs | Memory ICs |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Uri ng Memory | Configuration EPROM (UV-erasable, OTP variant) | OTP Configuration PROM (non-volatile) |
| Laki ng Memory | 440,800 bits | 212 Kbit |
| Usable Configuration Bits | 433,008 bits | — |
| Configuration Interface | Altera serial / JTAG configuration bus | — |
| Volte ng Pagbibigay | 3.3 V or 5.0 V | — |
| Programming Method | JTAG in-system programmer (Altera Quartus II) | — |
| Cascade Support | Yes (multi-FPGA chain) | Yes (nCASC pin for multi-device chains) |
| Packhaging | TSSOP-20 | 20-PLCC (9x9 mm), J-lead |
| Temperature na Operasyon | -40 C to +85 C (industrial grade) | -40C to +85C (industrial) |
| Tindminan RoHS | unknown | [DATA_NEEDED: RoHS status - legacy Altera part] |
| Lead-Free | unknown | [DATA_NEEDED: lead-free status] |
| Bilang ng Pin | 20 | 20 |
| Compatible FPGAs | Altera FLEX 10K, APEX 20K, ACEX 1K families | — |
| Manufacturer | Altera (now Intel FPGA) | — |
| Katayuan ng Lifecycle | Obsolete / Last Time Buy (per distributor stock) | — |
| Uri ng Interface | — | Serial (Altera active-serial configuration) |
| Supply Voltage (VCC) | — | 3.3 V / 5 V |
| I/O Voltage Tolerance | — | 3.3 V or 5 V |
| Programmability | — | OTP (one-time programmable) |
| Compatible FPGA Families | — | ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX |
| Configuration Mode | — | Active Serial (AS) |
| Internal Oscillator | — | Yes (generates DCLK to FPGA) |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |