EPC16QC100DM vs EPC40C100 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPC16QC100DM sa pamamagitan ng Intel at EPC40C100 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPC16QC100DM EPC40C100
Brand Intel Altera
Kategorya Memory ICs FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Uri ng Memory Non-volatile Configuration PROM (NOR flash) NOR Flash
Memory Density 16 Mbit (2 Mbyte) 40 Mbit
Configuration Interface Serial (SPI-compatible, Altera FPP mode) —
Core Supply Voltage (VCC) 3.0 V to 3.6 V —
I/O Voltage (VIO) 2.5 V / 3.3 V selectable —
Output Voltage (VPP) 1.8 V / 2.5 V / 3.3 V selectable —
Maximum DCLK Frequency 40 MHz —
Cascadable Yes (multi-device daisy chain via nCASC) —
In-System Programming Yes (IEEE 1532 / JTAG) —
Program/Erase Cycles [DATA_NEEDED: program/erase cycle endurance] —
Data Retention [DATA_NEEDED: data retention years] —
Hanay ng Temperature na Operasyon -40 C to +85 C (industrial) -40 C to +85 C (industrial)
Packhaging 100-pin PQFP (QFPA) 100-pin EQFP (Enhanced Quad Flat Pack)
Package Code Q100 + DM suffix —
Lead-Free / RoHS [DATA_NEEDED: lead-free status] —
Compatible FPGA Families Stratix, Cyclone, APEX, ACEX —
Level ng MSL [DATA_NEEDED: MSL rating] 3 (168 hours)
Device Family — Enhanced Configuration Device
Target FPGAs — Stratix, Cyclone, APEX, Mercury, ACEX families
Configuration Mode — FPP (Fast Passive Parallel) / PS (Passive Serial)
Interface Voltage — 2.5 V / 3.3 V
Maximum FPP Clock Frequency — 66 MHz
Programmability — In-system programmable (JTAG)
Error Detection — Built-in CRC verification
Pin Pitch — 0.5 mm
Uri ng Pagpapasok — Surface Mount
Tindminan RoHS — Compliant
Lead-Free — Yes

Mga Datasheets at Resources

Tingnan ang Lahat ng mga Produkto Lumikha ng BOM Hilingin ang Kita