EPC2LC20-T vs EPC2LC20-V Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPC2LC20-T sa pamamagitan ng Altera at EPC2LC20-V sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPC2LC20-T | EPC2LC20-V |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | Memory ICs | Memory ICs |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Uri ng Memory | Configuration PROM (Flash) | Configuration PROM (Flash-based, in-system programmable) |
| Laki ng Memory | 1.6 Mb | — |
| Configuration Mode | Serial (PS mode), cascadable | — |
| Max Configuration Frequency | 10 MHz | — |
| Volte ng Pagbibigay | 3.3 V (typical) | — |
| Programmability | In-System Programmable via JTAG | — |
| JTAG Interface | IEEE Std 1149.1-1990 compliant | — |
| Supported FPGA Families | ACEX, APEX, Cyclone, FLEX, MAX 7000A/B, MAX II, Mercury | APEX 20K, ACEX 1K, FLEX 10K, FLEX 6000, MAX 9000 |
| Cascade Support | Yes (nCASC pin) | Yes, daisy-chainable for >1.6 Mbit designs |
| Temperature na Operasyon | -40C to +85C (industrial) | — |
| Packhaging | 20-PLCC (9x9 mm) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (PLCC socket compatible) |
| Packaging Suffix | -T = Tape and Reel | — |
| Tindminan RoHS | Compliant | Compliant (per distributor listings) |
| Lead-Free | Yes | Yes |
| Memory Density | — | 1.6 Mbit |
| Configuration Interface | — | Serial (Altera FPP/PS modes via DCLK/nSTATUS/CONF_DONE) |
| Maximum Configuration Clock | — | 10 MHz |
| Supply Voltage VCC | — | 3.3 V |
| I/O Tolerance | — | 5 V tolerant on configuration pins |
| In-System Programming | — | Yes, via IEEE 1149.1 JTAG (TMS/TCK/TDI/TDO) |
| Operating Temperature Range (V suffix) | — | 0 °C to +70 °C (commercial) |
| Package Type | — | 20-pin PLCC (JEDEC MS-018) |
| Package Dimensions | — | 9 x 9 mm body, 1.27 mm pitch |