EPC2LC20NU vs EPC2LC20N-W Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPC2LC20NU sa pamamagitan ng Altera at EPC2LC20N-W sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPC2LC20NU EPC2LC20N-W
Brand Altera Altera
Kategorya Memory ICs Memory ICs
Katayuan ng Lifecycle Obsolete Obsolete
Fungsi In-System Programmable Configuration PROM —
Memory Density 1.6 Mbit —
FPGA Interface Altera serial (4-pin: nCS, DCLK, DATA, nINIT_CONF) —
Supply Voltage (VCC) 3.0 V to 3.6 V 3.0 V to 3.6 V, 4.75 V to 5.25 V
I/O Tolerance 5 V tolerant inputs (per datasheet, except JTAG pins) —
Programming Method In-system via IEEE 1149.1 JTAG —
JTAG Support Yes (IEEE Std 1149.1 boundary-scan compliant) —
Cascade Support Yes - daisy-chain for larger bitstreams Yes (with other EPC2 devices)
Minimum DC Input -0.3 V (inputs may undershoot to -2.0 V for <20 ns) —
Maximum Overshoot 7.0 V for <100 mA and <20 ns —
Packhaging 20-pin J-lead PLCC (9x9 mm) 20-LCC (J-Lead) PLCC-20
Uri ng Pagpapasok Surface Mount Surface Mount
Lead-Free / RoHS Non-LEAD / non-RoHS (NU suffix = matte tin Sn finish, not Pb-free) [DATA_NEEDED: RoHS status for -W variant]
Temperature na Operasyon 0C to +70C (commercial) [DATA_NEEDED: operating temperature range]
Compatibility Altera APEX 20K, APEX II, Mercury, FLEX 10K, ACEX 1K, Cyclone (legacy serial configuration) —
Uri ng Memory — EPROM (UV-erasable, ISP)
Laki ng Memory — 1.6 Mbit
Programmable Type — In System Programmable
Configuration Interface — Serial (DATA, DCLK, OE, nCS)
Internal Oscillator Frequency — 66.7 MHz
ISP Interface — JTAG (IEEE 1149.1)
Supported FPGA Families — APEX 20K, ACEX 1K, Mercury, FLEX 10K, Stratix, Cyclone
Packaging — Tape & Reel (-W suffix)
Bilang ng Pin — 20

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