EPC2LI20J vs EPC2LI20PULLS Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPC2LI20J sa pamamagitan ng Altera at EPC2LI20PULLS sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPC2LI20J | EPC2LI20PULLS |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | Memory ICs | Memory ICs |
| Katayuan ng Lifecycle | Aktibo | Obsolete |
| Uri ng Memory | In-System Programmable Configuration PROM (flash) | Serial Configuration Flash PROM |
| Laki ng Memory | 1,695,680 bits (1.6Mb) | 1.6 Mbit |
| Organisasyon | 65,536 x 1-bit (serial interface) | — |
| Interface | Altera 4-pin serial configuration (DATA, DCLK, nCS, nCONFIG) | — |
| Target FPGAs | APEX II, APEX 20K/20KC/20KE, Mercury, ACEX 1K, FLEX 6000/10KE/10KA | — |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V (3.3 V typical) | — |
| I/O Voltage (VCCIO) | 5.0 V or 3.3 V tolerant | — |
| ISP Programming Interface | JTAG (IEEE 1149.1) | — |
| Cascade Support | Yes (multi-device configuration chain) | — |
| Internal Oscillator | Yes (configures without external clock source) | — |
| Packhaging | 20-pin PLCC with J-leads (JEDEC MS-018) | 20-pin PLCC (J-Lead, 9x9 mm) |
| Temperature na Operasyon | -40C to +85C (industrial) | -40C to +85C (industrial) |
| Programming Cycles | [DATA_NEEDED: minimum endurance cycles] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | [DATA_NEEDED: lead-free finish] |
| Configuration Clock (DCLK) | Up to 33 MHz | — |
| Configuration Interface | — | Serial (Altera FPP / PS modes) |
| Maksimum na Taktiko ng Oras | — | 10 MHz |
| Supply Voltage (VCC) | — | 3.0 V to 3.6 V (3.3 V typical) |
| I/O Tolerance | — | 5 V tolerant configuration pins |
| Programmability | — | In-system via IEEE 1149.1 JTAG |
| Compression Support | — | Yes (real-time decompression in target FPGA) |
| Multi-Device Cascade | — | Yes (daisy-chain supported) |
| Uri ng Pagpapasok | — | Surface Mount / Socket |
| Level ng MSL | — | 3 (168 hours) |
| Compatible FPGA Families | — | Cyclone, Stratix, APEX, ACEX, Mercury, Excalibur |