EPF10K130EBC356-1N vs EPF10K130EBI356-2 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPF10K130EBC356-1N sa pamamagitan ng Altera at EPF10K130EBI356-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPF10K130EBC356-1N EPF10K130EBI356-2
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Family FLEX 10KE FLEX 10KE
Typical Gates 130,000 —
Maximum System Gates [DATA_NEEDED: maximum system gates for EPF10K130E] —
Logic Elements (LEs) 6,656 6,656
Embedded Array Blocks (EABs) [DATA_NEEDED: EAB count for EPF10K130E] —
Total RAM Bits 65,536 —
User I/O Pins 274 —
Packhaging 356-LBGA 356-LBGA (FineLine BGA)
Package Code LBGA —
Logic Family CMOS —
Process Technology 0.22 µm CMOS 0.22 um
Core Supply Voltage 2.5 V 2.5 V
I/O Supply Voltage 3.3 V 3.3 V (multi-voltage I/O banks)
Speed Grade -1 -2 (mid)
Propagation Delay 0.6 ns 0.6 ns
Maximum Internal Frequency 333.33 MHz —
Temperature na Operasyon 0 °C to 70 °C (Commercial) 0 C to +70 C (industrial "I")
JTAG Boundary-Scan IEEE Std. 1149.1-1990 compliant —
PCI Compliance PCI Local Bus Specification Rev. 2.2 (33/66 MHz, 3.3 V and 5.0 V) —
Uri ng Pagpapasok Surface Mount —
Tindminan RoHS [DATA_NEEDED: RoHS compliance for EPF10K130EBC356-1N] [DATA_NEEDED: RoHS compliance status]
System Gates — 130,000
Logic Array Blocks (LABs) — 832
Embedded Memory (EAB) — 65,536 bits
User I/Os — 274
Maximum Frequency — 333.33 MHz
Programming Interface — JTAG (IEEE 1149.1) / serial configuration
Configuration Mode — SRAM-based, in-system programmable

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