EPF10K130EBI356-2 vs EPF10K130EBC600-2 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPF10K130EBI356-2 sa pamamagitan ng Altera at EPF10K130EBC600-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPF10K130EBI356-2 | EPF10K130EBC600-2 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | NRND |
| Family | FLEX 10KE | FLEX-10KE |
| System Gates | 130,000 | — |
| Logic Elements (LEs) | 6,656 | — |
| Logic Array Blocks (LABs) | 832 | 832 |
| Embedded Memory (EAB) | 65,536 bits | 4 kbit per EAB |
| User I/Os | 274 | 424 |
| Packhaging | 356-LBGA (FineLine BGA) | 600-BGA (45 x 45 mm) |
| Process Technology | CMOS 0.22 um | SRAM CMOS, 0.25 um |
| Core Supply Voltage | 2.5 V | — |
| I/O Supply Voltage | 3.3 V (multi-voltage I/O banks) | — |
| Propagation Delay | 0.6 ns | — |
| Maximum Frequency | 333.33 MHz | — |
| Temperature na Operasyon | 0 C to +70 C (industrial "I") | 0 C to +70 C (Commercial) |
| Speed Grade | -2 (mid) | -2 |
| Programming Interface | JTAG (IEEE 1149.1) / serial configuration | — |
| Configuration Mode | SRAM-based, in-system programmable | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | Compliant |
| Typical Gates | — | 130,000 |
| Core Voltage (VCCINT) | — | 2.375 V to 2.625 V (2.5 V nominal) |
| I/O Voltage (VCCIO) | — | MultiVolt: 1.8 V / 2.5 V / 3.3 V |
| Pin-to-Pin Delay | — | 0.5 ns |
| Uri ng Pagpapasok | — | Surface Mount |
| Configuration Method | — | Serial / Parallel / JTAG |
| Level ng MSL | — | 3 (168 hours) |
| Supply Current (Quiescent) | — | 10 mA typical |