EPF10K200EFC672-2 vs EPF10K200SFC672-2 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPF10K200EFC672-2 sa pamamagitan ng Intel at EPF10K200SFC672-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPF10K200EFC672-2 | EPF10K200SFC672-2 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | NRND |
| Family | FLEX 10KE | — |
| Logic Elements | 9,984 | 9,984 |
| Typical Gates | 200,000 | — |
| Maximum User I/Os | 470 | — |
| Embedded Memory | 98,304 bits | — |
| Embedded Array Blocks (EABs) | 12 | — |
| Logic Array Blocks (LABs) | 624 | 1,248 |
| Packhaging | 672-BBGA (FineLine BGA) | 672-pin FineLine BGA (FBGA), 45 × 45 mm, 1.27 mm pitch |
| Package Dimensions | 45 x 45 mm | — |
| Ball Pitch | 1.27 mm | — |
| Process Technology | 0.22 um CMOS | 0.22 µm CMOS |
| Speed Grade | -2 | -2 |
| Propagation Delay | 0.4 ns | — |
| Temperature na Operasyon | 0 C to 70 C | 0 °C to +70 °C (Commercial) |
| Supply Voltage (Core) | [DATA_NEEDED: core Vcc] | — |
| Programmability | JTAG (IEEE 1149.1) / in-system | — |
| Tindminan RoHS | Compliant (per distributor listing) | [DATA_NEEDED: RoHS compliance status] |
| Logic Family | CMOS | — |
| Series | — | FLEX 10KE |
| System Gates | — | 200,000 |
| User I/O Pins | — | 470 |
| Embedded Memory (bits) | — | 98,304 |
| Core Supply Voltage | — | 2.5 V (2.375 V to 2.625 V) |
| I/O Supply Voltage | — | MultiVolt 2.5 V / 3.3 V / 5.0 V |
| Internal Propagation Delay | — | 0.4 ns |
| Maximum Operating Frequency | — | 200 MHz |
| Configuration Method | — | SRAM-based, passive parallel asynchronous |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |
| On-chip PLL | — | Yes |