EPF10K200SFC672-2 vs EPF10K200SFI672-2 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPF10K200SFC672-2 sa pamamagitan ng Altera at EPF10K200SFI672-2 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPF10K200SFC672-2 | EPF10K200SFI672-2 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Series | FLEX 10KE | — |
| Logic Elements | 9,984 | 9984 |
| System Gates | 200,000 | 200000 |
| Logic Array Blocks (LABs) | 1,248 | 1248 |
| User I/O Pins | 470 | — |
| Embedded Memory (bits) | 98,304 | — |
| Process Technology | 0.22 µm CMOS | 0.22 µm (Arrow lists 0.42 µm) |
| Core Supply Voltage | 2.5 V (2.375 V to 2.625 V) | 2.5 V |
| I/O Supply Voltage | MultiVolt 2.5 V / 3.3 V / 5.0 V | — |
| Speed Grade | -2 | -2 |
| Internal Propagation Delay | 0.4 ns | — |
| Maximum Operating Frequency | 200 MHz | — |
| Packhaging | 672-pin FineLine BGA (FBGA), 45 × 45 mm, 1.27 mm pitch | 672-pin FineLine BGA (FBGA) |
| Temperature na Operasyon | 0 °C to +70 °C (Commercial) | Industrial (-40C to +85C) |
| Configuration Method | SRAM-based, passive parallel asynchronous | — |
| Boundary Scan | IEEE 1149.1 (JTAG) | — |
| On-chip PLL | Yes | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | Not compliant (per Arrow EU RoHS listing) |
| Family | — | FLEX 10KE |
| User I/Os | — | 470 |
| Embedded Array Blocks (EABs) | — | 24 |
| Embedded Memory (EAB SRAM) | — | 96 Kbit |
| Distributed Memory | — | 98304 bits |
| JTAG Boundary Scan | — | IEEE Std. 1149.1-1990 compliant |
| PCI Compliance | — | PCI Local Bus Specification Rev 2.2 (3.3 V, 33/66 MHz) on -1 speed grade |
| Programming | — | SRAM-based, in-system programmable |