EPF6010ATC100-2 vs EPF6010ATC100-1 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPF6010ATC100-2 sa pamamagitan ng Altera at EPF6010ATC100-1 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPF6010ATC100-2 - FLEX 6000 FPGA, 880 Gates, 71 I/O | Intel (Altera)
EPF6010ATC100-2 ObsoletePagsanggunian na paghahambing
| Parametro | EPF6010ATC100-2 | EPF6010ATC100-1 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Series | FLEX 6000 | — |
| Family | SRAM-based FPGA | FLEX 6000 |
| Manufacturer | Intel (formerly Altera) | — |
| Logic Elements / Gates | 880 gates (typical) | — |
| Logic Array Blocks (LABs) | 88 | 88 |
| User I/O Pins | 71 | — |
| Number of Logic Cells | 880 (per FLEX 6000 family datasheet) | — |
| Packhaging | 100-pin TQFP (14x14 mm) | 100-pin TQFP |
| Speed Grade | -2 | — |
| Temperature na Operasyon | 0C to 70C (commercial) | -40°C to +85°C (industrial) |
| Core Supply Voltage | 3.0 V to 3.6 V (typical 3.3 V) | 3.3 V |
| I/O Supply Voltage | 3.3 V (5 V tolerant inputs per FLEX 6000 family) | — |
| Configuration Interface | JTAG (IEEE 1149.1) + serial configuration | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Level ng MSL | [DATA_NEEDED: moisture sensitivity level] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Process Node | [DATA_NEEDED: CMOS process node] | — |
| Total RAM Bits | [DATA_NEEDED: embedded RAM] | — |
| Logic Elements | — | 880 |
| Typical Gates | — | 10,000 |
| Maximum User I/O | — | 71 |
| Maximum Toggle Rate | — | 200 MHz |
| Process Technology | — | 0.42 µm CMOS |
| I/O Tolerance | — | 5 V tolerant |
| Configuration Mode | — | Passive Serial (PS) |
| Program Memory Type | — | SRAM |
| JTAG Support | — | IEEE 1149.1 boundary scan |