EPF6016TI144-3N vs EPF6016ATI144-2N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPF6016TI144-3N sa pamamagitan ng Intel at EPF6016ATI144-2N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPF6016TI144-3N - FLEX 6000 FPGA, 16K Gates, 144-LQFP | Intel / Altera
EPF6016TI144-3N Obsolete
Pagsanggunian na paghahambing
| Parametro | EPF6016TI144-3N | EPF6016ATI144-2N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | FLEX 6000 | FLEX 6000 |
| Logic Elements | 1,320 | — |
| Usable Gates | 16,000 | — |
| Logic Array Blocks (LABs) | 132 | — |
| User I/O | 117 | — |
| Bilang ng Pins | 144 | — |
| Packhaging | 144-LQFP (TQFP), gull-wing, 20 mm body | 144-pin TQFP (TQ144, 22 mm × 22 mm) |
| Process Technology | 0.42 µm CMOS, SRAM-based | — |
| Core Supply Voltage (VCCINT) | 5.0 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V or 5.0 V (MultiVolt) | — |
| Internal Operating Frequency | 125 MHz (max) | — |
| Speed Grade | -3 (faster than -4, slower than -2) | — |
| Temperature na Operasyon | 0 °C to +85 °C (industrial, 'N' suffix) | — |
| Configuration Method | Serial EPROM or JTAG (SRAM-based) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Logic Elements (LEs) | — | 1,320 |
| Typical Gates | — | 16,000 |
| Maximum Gates | — | 24,000 |
| Maximum Internal Frequency | — | 166.67 MHz |
| Technology Node | — | 0.42 µm CMOS |
| User I/O Pins | — | 117 |
| Dedicated Inputs | — | 4 |
| Core Voltage (VCCINT) | — | 3.3 V (3.0 V – 3.6 V) |
| I/O Voltage (VCCIO) | — | 3.3 V (5.0 V tolerant inputs supported) |
| Operating Temperature (Industrial, -2 speed grade) | — | -40 °C to +100 °C |
| Lead Pitch | — | 0.500 mm |
| Programming Interface | — | JTAG (IEEE 1149.1) / Altera ByteBlaster |