EPF8636ARC208-3 vs EPF8820ARC208-3 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPF8636ARC208-3 sa pamamagitan ng Altera at EPF8820ARC208-3 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPF8820ARC208-3 - FLEX 8000 FPGA, 8K Gates, 672 Cells | Intel / Altera
EPF8820ARC208-3 ObsoletePagsanggunian na paghahambing
| Parametro | EPF8636ARC208-3 | EPF8820ARC208-3 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Series | FLEX 8000 | FLEX 8000 |
| Family | FLEX 8000 (FLEX 8K) | FLEX 8000 (EPF8820) |
| Typical Gate Count | 6,000 gates | — |
| Logic Elements / Cells | 504 | — |
| Number of User I/O | 136 | — |
| Operating Frequency (max) | 125 MHz | — |
| Volte ng Pagbibigay | 4.75 V to 5.25 V (5 V nominal) | — |
| Technology | CMOS SRAM, 0.42 um process | — |
| Speed Grade | -3 | — |
| Packhaging | 208-RQFP (28x28 mm) with exposed pad | — |
| Package Category | 208-BFQFP Exposed Pad | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | 0 C to +70 C (commercial) | — |
| Tindminan RoHS | Non-compliant per distributor listing | [DATA_NEEDED: RoHS status] |
| Configuration Method | SRAM, loaded via serial EPROM or download cable | — |
| Usable Gates | — | 8,000 |
| Logic Cells / Elements | — | 672 |
| Registers | — | 152 |
| Maximum Operating Frequency | — | 125 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Process Technology | — | 0.42 µm CMOS |
| Configuration Memory | — | SRAM (volatile) |
| Packhaging / Kaso | — | 208-BFQFP Exposed Pad (208-RQFP, 28x28 mm) |
| Supplier Device Package | — | 208-RQFP (28x28) |
| Packaging | — | Tray |
| Hanay ng Temperature na Operasyon | — | [DATA_NEEDED: operating temperature range] |
| In-Circuit Reconfigurability (ICR) | — | Yes (via external configuration devices) |
| Boundary-Scan Test | — | JTAG (IEEE 1149.1) |
| I/O Tolerance | — | 3.3 V / 5 V |
| Clock Networks | — | 4 dedicated low-skew global clocks |
| Lead-Free / Finish | — | [DATA_NEEDED: lead-free finish] |