EPF8820ARC208-5N vs EPF8820ARC208-3 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPF8820ARC208-5N sa pamamagitan ng Altera at EPF8820ARC208-3 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPF8820ARC208-3 - FLEX 8000 FPGA, 8K Gates, 672 Cells | Intel / Altera
EPF8820ARC208-3 ObsoletePagsanggunian na paghahambing
| Parametro | EPF8820ARC208-5N | EPF8820ARC208-3 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | FLEX 8000 | FLEX 8000 (EPF8820) |
| Logic Elements | 672 | — |
| Typical Gates | 8,000 | — |
| User I/O Pins | 152 | — |
| Process Technology | 0.42 µm CMOS | 0.42 µm CMOS |
| Core Supply Voltage | 5 V | — |
| Speed Grade | -5 (slowest commercial) | — |
| Packhaging | 208-pin RQFP Exposed Pad | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Configuration Method | SRAM, parallel EPROM or serial EPC | — |
| Configuration Devices Supported | EPC1, EPC1064, EPC1213, EPC1441 | — |
| Temperature na Operasyon | 0 °C to +70 °C (commercial) | — |
| Tindminan RoHS | Lead free / RoHS Compliant | [DATA_NEEDED: RoHS status] |
| Programming Interface | JTAG-compatible (ByteBlaster) | — |
| Device Family Tier | FLEX 8000 (legacy) | — |
| Series | — | FLEX 8000 |
| Usable Gates | — | 8,000 |
| Logic Cells / Elements | — | 672 |
| Registers | — | 152 |
| Maximum Operating Frequency | — | 125 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Configuration Memory | — | SRAM (volatile) |
| Packhaging / Kaso | — | 208-BFQFP Exposed Pad (208-RQFP, 28x28 mm) |
| Supplier Device Package | — | 208-RQFP (28x28) |
| Packaging | — | Tray |
| Hanay ng Temperature na Operasyon | — | [DATA_NEEDED: operating temperature range] |
| In-Circuit Reconfigurability (ICR) | — | Yes (via external configuration devices) |
| Boundary-Scan Test | — | JTAG (IEEE 1149.1) |
| I/O Tolerance | — | 3.3 V / 5 V |
| Clock Networks | — | 4 dedicated low-skew global clocks |
| Lead-Free / Finish | — | [DATA_NEEDED: lead-free finish] |