EPM2210F256C5 vs EPM2210F256I5 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM2210F256C5 sa pamamagitan ng Altera at EPM2210F256I5 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM2210F256C5 - MAX II CPLD 1700 Macrocells 201MHz FBGA-256 | Altera / Intel
EPM2210F256C5 NrndPagsanggunian na paghahambing
| Parametro | EPM2210F256C5 | EPM2210F256I5 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Aktibo |
| Device Family | MAX II | — |
| Series | EPM2210 | MAX II CPLD |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macro Cells (Logic Elements) | 1700 | — |
| Maximum Internal Frequency | 201.1 MHz | 201.1 MHz |
| Propagation Delay | 5 ns (C5 speed grade) | — |
| User I/Os | 272 | — |
| Volte ng Pagbibigay | 2.5 V / 3.3 V (MultiVolt I/O) | — |
| Process Technology | 0.18 µm flash-based | — |
| Packhaging | 256-ball FineLine BGA (FBGA-256) | — |
| Package Code | BGA, 17 x 17 mm, 1.0 mm pitch | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | 0C to +85C (commercial, C5 suffix) | — |
| Programming Interface | JTAG (IEEE 1149.1), in-system programmable | — |
| Configuration Memory | On-chip flash (instant-on, non-volatile) | — |
| On-chip User Flash Memory | 8 Kbits | — |
| Tindminan RoHS | Compliant | Non-compliant (contains lead, per IC Components datasheet) |
| Level ng MSL | 3 (per JEDEC J-STD-020) | — |
| Family | — | MAX II |
| Number of Macrocells | — | 1700 |
| Number of Logic Elements | — | 2210 |
| Maximum Propagation Delay (tpd) | — | 7.0 ns |
| Supply Voltage - Internal | — | 2.5 V, 3.3 V |
| Operating Temperature (TJ) | — | -40 C to +100 C |
| Packhaging / Kaso | — | 256-FBGA (17x17) |
| Programmable I/O Pins | — | [DATA_NEEDED: number of user I/O pins] |
| User Flash Memory | — | 8 Kbit |
| Number of Logic Array Blocks | — | 16 |
| I/O Voltage Standards | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| JTAG Compliant | — | Yes (IEEE 1149.1) |
| In-System Programmable | — | Yes (via ByteBlaster/USB-Blaster) |
| Delivery Type | — | Tray |