EPM240GT100I5 vs EPM240GT100I5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM240GT100I5 sa pamamagitan ng Intel at EPM240GT100I5N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM240GT100I5 | EPM240GT100I5N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | MAX II | MAX II |
| Logic Elements | 240 | — |
| Equivalent Macrocells | 192 | 192 |
| User I/O Pins | 80 | — |
| Propagation Delay (tPD) | 7.5 ns | 4.7 ns |
| User Flash Memory (UFM) | 8 Kbits | — |
| Process Technology | 0.18 um, 6-layer-metal flash | 0.18 µm 6-layer-metal Flash CMOS |
| Temperature na Operasyon | -40C to +100C (industrial) | -40 °C to +100 °C (Industrial) |
| Packhaging | TQFP-100 (GT100) | 100-pin TQFP (14x14 mm, 0.5 mm pitch) |
| Package Body Size | 16 mm x 16 mm | — |
| Lead Pitch | 0.50 mm | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Supply Voltage (Core) | 3.0 V to 3.6 V (VCCINT) | — |
| I/O Voltage (VCCIO) | 1.8 V / 2.5 V / 3.3 V (MultiVolt) | — |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | JTAG (IEEE 1149.1) ISP |
| Tindminan RoHS | Compliant | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Elements (LEs) | — | 240 |
| User I/Os | — | 80 |
| Internal Performance (fMAX) | — | 304 MHz |
| Embedded Non-Volatile Memory | — | 8 Kbits user Flash |
| Supply Voltage - Core (VCCINT) | — | 1.71 V to 1.89 V (3.3 V tolerant for MAX II G variant) |
| I/O Bank Voltage (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V MultiVolt I/O |
| Lead-Free / RoHS | — | Yes (suffix N) |