EPM240GT100I5 vs EPM240T100C5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM240GT100I5 sa pamamagitan ng Intel at EPM240T100C5N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM240GT100I5 | EPM240T100C5N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | MAX II | MAX II |
| Logic Elements | 240 | — |
| Equivalent Macrocells | 192 | 192 |
| User I/O Pins | 80 | — |
| Propagation Delay (tPD) | 7.5 ns | — |
| User Flash Memory (UFM) | 8 Kbits | — |
| Process Technology | 0.18 um, 6-layer-metal flash | 0.18 µm, 6-layer-metal flash |
| Temperature na Operasyon | -40C to +100C (industrial) | 0 °C to +85 °C (commercial, 'C' suffix) |
| Packhaging | TQFP-100 (GT100) | 100-pin TQFP (T100), 14x14 mm |
| Package Body Size | 16 mm x 16 mm | — |
| Lead Pitch | 0.50 mm | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Supply Voltage (Core) | 3.0 V to 3.6 V (VCCINT) | — |
| I/O Voltage (VCCIO) | 1.8 V / 2.5 V / 3.3 V (MultiVolt) | — |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | JTAG (IEEE 1149.1) / ISP |
| Tindminan RoHS | Compliant | Compliant (lead-free) |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Elements (LEs) | — | 240 |
| On-Chip User Flash | — | 8 Kbits |
| Maximum User I/O Pins | — | 80 |
| Number of I/O Banks | — | 4 |
| Pin-to-Pin Delay (speed grade 5) | — | 4.7 ns |
| Maximum Internal Frequency | — | 201.1 MHz |
| Core Supply Voltage (VCCINT) | — | 2.5 V / 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) |