EPM240M100C5N vs EPM240GM100C5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM240M100C5N sa pamamagitan ng Intel at EPM240GM100C5N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM240GM100C5N - 192-Cell MAX II G CPLD, 4.7ns, 100-MBGA | Intel / Altera
EPM240GM100C5N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EPM240M100C5N | EPM240GM100C5N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Aktibo |
| Family | MAX II | MAX II G |
| Logic Elements | 240 | 240 (192 macrocells) |
| Macrocells | 192 | — |
| User I/Os | 80 | 80 |
| Propagation Delay (tPD) | 4.7 ns | — |
| User Flash Memory | 8 Kbits | — |
| Supply Voltage - Core | 1.8 V | 3.3 V |
| Supply Voltage - I/O | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Temperature na Operasyon | -40 C to +125 C | -40 C to +125 C |
| Packhaging | 100-ball MBGA (Micro FBGA), 6 x 6 mm, 0.5 mm pitch | 100-MBGA (Micro FineLine BGA), 6 x 6 mm |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (BGA) |
| Process Technology | 0.18 µm CMOS | CMOS, Flash-based |
| Configuration Memory | On-chip Flash (non-volatile) | Non-volatile Flash |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| Tindminan RoHS | Compliant (lead-free) | — |
| Logic Family | CMOS | — |
| Pin-to-Pin Delay (tPD) | — | 4.7 ns |
| Ball Pitch | — | 0.5 mm |
| I/O Voltage Support | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (multiVolt) |
| Programming Interface | — | JTAG (IEEE 1149.1) - ISP |
| Lead Free / RoHS | — | Yes / Compliant |
| Level ng MSL | — | 3 |