EPM240T100A5N vs EPM240T100C5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM240T100A5N sa pamamagitan ng Altera at EPM240T100C5N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM240T100A5N - 192-Macrocell MAX II CPLD, 100-TQFP | Intel / Altera
EPM240T100A5N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EPM240T100A5N | EPM240T100C5N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | MAX II | MAX II |
| Macro Cells | 192 | — |
| Logic Elements (LE) | 240 | — |
| User I/O Count | 80 | — |
| Pin-to-Pin Logic Delay (tPD) | 4.7 ns | — |
| Maximum Internal Frequency | 201.1 MHz | 201.1 MHz |
| Volte ng Pagbibigay | 2.5 V / 3.3 V | — |
| I/O Bank Count | 4 (multi-voltage) | — |
| Process Technology | 0.18 µm | 0.18 µm, 6-layer-metal flash |
| Configuration Memory | On-chip Flash (instant-on) | — |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | JTAG (IEEE 1149.1) / ISP |
| Packhaging | 100-pin TQFP (14 x 14 x 1.0 mm) | 100-pin TQFP (T100), 14x14 mm |
| Temperature na Operasyon | 0C to +85C (commercial, "A5N" suffix) | 0 °C to +85 °C (commercial, 'C' suffix) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | Compliant (Pb-free) | Compliant (lead-free) |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Elements (LEs) | — | 240 |
| Equivalent Macrocells | — | 192 |
| On-Chip User Flash | — | 8 Kbits |
| Maximum User I/O Pins | — | 80 |
| Number of I/O Banks | — | 4 |
| Pin-to-Pin Delay (speed grade 5) | — | 4.7 ns |
| Core Supply Voltage (VCCINT) | — | 2.5 V / 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) |