EPM240T100C3N vs EPM240T100A5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM240T100C3N sa pamamagitan ng Altera at EPM240T100A5N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM240T100A5N - 192-Macrocell MAX II CPLD, 100-TQFP | Intel / Altera
EPM240T100A5N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EPM240T100C3N | EPM240T100A5N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Series | MAX II | — |
| Device Family | MAX II CPLD (EPM240) | — |
| Logic Elements (LE) | 240 | 240 |
| Macrocells | 192 | — |
| User I/O Pins | 80 | — |
| User Flash Memory (UFM) | 8 Kbits | — |
| Packhaging | 100-pin TQFP (14x14 mm) | 100-pin TQFP (14 x 14 x 1.0 mm) |
| Configuration Memory | Internal Flash (non-volatile) | On-chip Flash (instant-on) |
| Pin-to-Pin Logic Delay (tPD) | 4.4 ns (typical) | 4.7 ns |
| Maximum Operating Frequency | 200 MHz (internal oscillator) | — |
| Core Supply Voltage (VCCINT) | 3.0 V to 3.6 V | — |
| I/O Supply Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | JTAG (IEEE 1149.1) / ISP |
| Temperature na Operasyon | 0 °C to +85 °C (commercial) | 0C to +85C (commercial, "A5N" suffix) |
| Quiescent Current (typical) | 35 mA | — |
| Tindminan RoHS | Compliant | Compliant (Pb-free) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Level ng MSL | [DATA_NEEDED: MSL rating] | — |
| Family | — | MAX II |
| Macro Cells | — | 192 |
| User I/O Count | — | 80 |
| Maximum Internal Frequency | — | 201.1 MHz |
| Volte ng Pagbibigay | — | 2.5 V / 3.3 V |
| I/O Bank Count | — | 4 (multi-voltage) |
| Process Technology | — | 0.18 µm |