EPM240T100C4N vs EPM240T100I3N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM240T100C4N sa pamamagitan ng Altera at EPM240T100I3N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPM240T100I3N - 192-Macrocell MAX II CPLD, 100-TQFP, Industrial | Intel
EPM240T100I3N ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EPM240T100C4N | EPM240T100I3N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Huling Pagbili |
| Family | MAX II | MAX II |
| Device | EPM240 | — |
| Macro Cells | 192 | — |
| Logic Elements | 240 | — |
| Propagation Delay (tPD) | 4.7 ns (max) | — |
| Maximum Frequency | 247.5 MHz | — |
| User I/O | 80 | — |
| Supply Voltage - Internal | 2.5 V / 3.3 V | — |
| I/O Voltage (MultiVolt) | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Process Technology | 0.18 µm | — |
| Programmable Type | In-System Programmable (Flash) | — |
| Packhaging / Kaso | 100-TQFP | — |
| Uri ng Pagpapasok | Surface Mount | — |
| Temperature na Operasyon | 0 °C to +85 °C (commercial, 'C' suffix) | — |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| Tindminan RoHS | Compliant (lead-free, 'N' suffix) | Compliant |
| Device Logic Elements / Macrocells | — | 192 macrocells |
| Maximum User I/O Pins | — | 80 |
| Number of Logic Array Blocks (LABs) | — | 4 |
| On-chip User Flash Memory | — | 8 Kbits |
| Internal Performance | — | 304 MHz |
| Pin-to-pin Logic Delay (tPD1) | — | 4.6 ns |
| Global Clock Networks | — | 4 |
| Technology Node | — | 0.18 um, 6-layer-metal flash CMOS |
| Supply Voltage - Core | — | 2.5 V / 3.3 V |
| MultiVolt I/O Support | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Temperature ng Junction na Operasyon | — | -40C to +100C (industrial, 'I' grade) |
| Speed Grade | — | 3 |
| Packhaging | — | TQFP-100 (T100), 14x14 mm, 0.5 mm pitch |
| Programming Interface | — | JTAG / IEEE 1149.1 ISP |
| Instant-on (non-volatile) | — | Yes (flash-based) |
| Level ng MSL | — | 3 (per JEDEC J-STD-020) |