EPM3032ALC44-4 vs EPM3032ALC44-10 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3032ALC44-4 sa pamamagitan ng Altera at EPM3032ALC44-10 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPM3032ALC44-10 - MAX 3000A CPLD, 32 Macrocells, 10ns, 44-PLCC | Intel / Altera
EPM3032ALC44-10 ObsoletePagsanggunian na paghahambing
| Parametro | EPM3032ALC44-4 | EPM3032ALC44-10 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 32 | 32 |
| Logic Array Blocks (LABs) | 2 | 2 |
| User I/O Pins | 34 | — |
| Pin-to-Pin Delay (tPD) | 4.5 ns | 10 ns |
| Maximum Counter Frequency | 227.3 MHz | 227.3 MHz |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V (MultiVolt: 5.0 V / 3.3 V / 2.5 V compatible) | — |
| Usable Gates | 600 to 10,000 (MAX 3000A family range) | 600 |
| Packhaging | 44-pin PLCC (J-Lead) | 44-pin PLCC (J-Lead) |
| Temperature na Operasyon | 0°C to +70°C (Commercial) | 0C to +70C (commercial) |
| Technology | CMOS EEPROM-based | — |
| In-System Programmability (ISP) | Yes, IEEE Std. 1532 compliant | — |
| Boundary-Scan Test | IEEE Std. 1149.1 (JTAG) | — |
| Programming Interface | JTAG (ByteBlaster / MasterBlaster) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | — |
| Uri ng Pagpapasok | Surface Mount (PLCC J-Lead) | Surface Mount / Socket |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Maximum User I/O Pins | — | 34 |
| Supply Voltage (VCCINT) | — | 3.3 V |
| In-System Programming | — | Yes - JTAG (IEEE Std. 1149.1) |
| Concurrent ISP | — | Yes - IEEE Std. 1532 |
| Process Technology | — | CMOS EEPROM |