EPM3032ATC44-10AA vs EPM3032ALI44-10N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3032ATC44-10AA sa pamamagitan ng Intel at EPM3032ALI44-10N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM3032ATC44-10AA | EPM3032ALI44-10N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Series | MAX 3000A | — |
| Family | CPLD - Complex Programmable Logic | MAX 3000A |
| Macro Cells | 32 | — |
| Logic Array Blocks (LABs) | 2 | — |
| Usable Gates | 600 | — |
| Number of I/O | 34 | 34 |
| Propagation Delay (tPD) | 10 ns (max, -10 speed grade) | — |
| Counter Frequency | 227.3 MHz (max) | 227.3 MHz |
| Supply Voltage - Core (VCCINT) | 3.0 V to 3.6 V (3.3 V nominal) | — |
| Supply Voltage - I/O (VCCIO) | 2.5 V / 3.3 V / 5.0 V selectable | — |
| Temperature na Operasyon | 0C to +70C (commercial, 'C' suffix) | — |
| Packhaging | 44-TQFP (10 mm x 10 mm) | 44-LCC (J-Lead), PLCC-44 |
| Uri ng Pagpapasok | Surface Mount | — |
| Programmable Type | EEPROM (in-system programmable) | In System Programmable (ISP) |
| JTAG Interface | IEEE Std. 1149.1 boundary scan + IEEE Std. 1532 ISP | — |
| Tindminan RoHS | Compliant (lead-free 'A' suffix) | Non-Compliant |
| Number of Macrocells | — | 32 |
| Number of Usable Gates | — | 600 |
| Logic Elements / Blocks | — | 2 |
| Pin-to-Pin Delay (tPD) | — | 10 ns (speed grade -10) |
| Core Supply Voltage | — | 3.3 V |
| I/O Voltage Support (MultiVolt) | — | 5.0 V / 3.3 V / 2.5 V |
| Program Memory Type | — | EEPROM (non-volatile) |
| Programming Interface | — | IEEE Std. 1149.1 JTAG |
| Operating Temperature Grade | — | Industrial |
| Lead Free Status | — | Contains Lead |
| PCI Compliance | — | PCI SIG Revision 2.2 (speed grades -4/-5/-6/-7/-10) |