EPM3064ATC100-10N vs EPM3064ATC100-7N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3064ATC100-10N sa pamamagitan ng Altera at EPM3064ATC100-7N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3064ATC100-10N EPM3064ATC100-7N
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Aktibo NRND
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD - Complex Programmable Logic Device
Macrocells 64 64
Logic Array Blocks (LABs) 2 2
Maximum User I/O Pins 66 —
Usable Gates 1,250 up to 1,250
Pin-to-Pin Delay (tPD) 10 ns —
Supply Voltage (VCCINT) 3.3 V (3.0 V to 3.6 V) —
In-System Programmability Yes - IEEE Std. 1149.1 JTAG, IEEE Std. 1532 —
Boundary-Scan Test (BST) Yes - JTAG compliant —
Configuration Memory Non-volatile EEPROM —
Program/Erase Cycles 100 minimum —
MultiVolt I/O Yes - 1.8 V / 2.5 V / 3.3 V / 5 V tolerant —
Temperature na Operasyon 0C to +70C (commercial) 0 °C to +70 °C (commercial)
Packhaging 100-pin TQFP TQFP-100
Uri ng Pagpapasok Surface Mount Surface Mount
Tindminan RoHS Compliant (lead-free) [DATA_NEEDED: confirmed RoHS status from manufacturer page]
User I/O Pins — 66
Propagation Delay (tPD) — 7.5 ns (pin-to-pin, -7 speed grade)
Maximum Internal Frequency — 166.7 MHz (-7 speed grade)
Core Supply Voltage (VCCINT) — 3.3 V
I/O Supply Voltage (VCCIO) — 3.3 V or 2.5 V
Program Memory Technology — EEPROM (non-volatile)
In-System Programming — IEEE Std. 1149.1 (JTAG), IEEE Std. 1532

Mga Datasheets at Resources

Tingnan ang Lahat ng mga Produkto Lumikha ng BOM Hilingin ang Kita