EPM3064ATC44-10 vs EPM3064ATI44-10NAD Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3064ATC44-10 sa pamamagitan ng Altera at EPM3064ATI44-10NAD sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3064ATC44-10 EPM3064ATI44-10NAD
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 3000A MAX 3000A
Logic Elements / Macrocells 64 macrocells —
Usable Gates 1,250 1,250
Number of Logic Blocks / LABs 4 LABs —
Propagation Delay (tPD) 10 ns —
Maximum Internal Frequency 227.3 MHz (counter speed) —
Programmable I/Os 34 —
Supply Voltage (VCCINT) 3.0 V to 3.6 V (3.3 V typical) —
I/O Bank Voltage (VCCIO) MultiVolt 1.5 V / 1.8 V / 2.5 V / 3.3 V —
Technology CMOS EEPROM, 5 V tolerant I/O —
In-System Programming IEEE Std. 1532 (JTAG) —
Boundary-Scan Support IEEE 1149.1 (JTAG) —
Packhaging TQFP-44, 10 x 10 mm, 0.8 mm pitch TQFP-44
Uri ng Pagpapasok Surface Mount Surface Mount
Hanay ng Temperature na Operasyon 0C to +70C (commercial) —
Tindminan RoHS Non-compliant (legacy Altera, Pb-bearing) Compliant
Macrocells — 64
Logic Array Blocks (LABs) — 4 (16 macrocells each)
User I/Os (max) — 34
Pin-to-Pin Delay (tPD) — 10 ns
Setup Time (tSU) — 4.5 ns
Core Voltage (VCCINT) — 3.3 V
I/O Voltage (VCCIO) — 3.3 V or 2.5 V
Temperature na Operasyon — -40C to +85C (Industrial)
Programming Interface — JTAG (IEEE Std. 1532 compliant)
In-System Programmable — Yes

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