EPM3064ATC44-4N vs EPM3064ATC44-10N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3064ATC44-4N sa pamamagitan ng Altera at EPM3064ATC44-10N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM3064ATC44-4N | EPM3064ATC44-10N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Aktibo |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 64 | 64 |
| Logic Array Blocks | 2 | — |
| Number of I/Os | 34 | — |
| Dedicated Inputs | 4 | — |
| Usable Gates | 1,250 | 1250 |
| Propagation Delay (tpd) | 4.5 ns | — |
| Maximum Counter Frequency | 222.2 MHz | 192.3 MHz |
| Supply Voltage (VCCINT) | 3.3 V | 3.3 V |
| I/O Supply Voltage (VCCIO) | 2.5 V or 3.3 V | — |
| Programmability | EEPROM, in-system programmable (JTAG) | — |
| JTAG Support | IEEE Std. 1149.1 (boundary-scan) and IEEE Std. 1532 (ISP) | — |
| Temperature na Operasyon | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Packhaging | 44-pin TQFP | TQFP-44 (10x10 mm) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | [DATA_NEEDED: rohs status] | Compliant |
| User I/O Pins | — | 34 |
| Logic Array Blocks (LABs) | — | 4 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| I/O Standard | — | MultiVolt (mixed 1.5 V / 1.8 V / 2.5 V / 3.3 V) |
| Configuration Memory | — | EEPROM (non-volatile) |
| In-System Programming | — | IEEE Std. 1532 compliant |
| Boundary-Scan Test | — | IEEE Std. 1149.1 (JTAG) compliant |
| Pin-Locking | — | Yes (across design iterations) |