EPM3064ATC44-4N vs EPM3064ATC44-10NAF Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3064ATC44-4N sa pamamagitan ng Altera at EPM3064ATC44-10NAF sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3064ATC44-4N EPM3064ATC44-10NAF
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND NRND
Family MAX 3000A —
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macro Cells 64 64
Logic Array Blocks 2 —
Number of I/Os 34 —
Dedicated Inputs 4 —
Usable Gates 1,250 1250
Propagation Delay (tpd) 4.5 ns —
Maximum Counter Frequency 222.2 MHz —
Supply Voltage (VCCINT) 3.3 V 3.0 V to 3.6 V
I/O Supply Voltage (VCCIO) 2.5 V or 3.3 V —
Programmability EEPROM, in-system programmable (JTAG) —
JTAG Support IEEE Std. 1149.1 (boundary-scan) and IEEE Std. 1532 (ISP) —
Temperature na Operasyon 0C to +70C (commercial) [DATA_NEEDED: industrial/commercial grade]
Packhaging 44-pin TQFP TQFP-44 (10x10 mm)
Uri ng Pagpapasok Surface Mount Surface Mount
Tindminan RoHS [DATA_NEEDED: rohs status] Compliant
Series — MAX 3000A
Logic Elements / LABs — 4 LABs (16 macrocells per LAB)
Number of I/O Pins — 34
Propagation Delay (tPD, max) — 10 ns
I/O Voltage Tolerance — Multi-voltage (3.3 V / 2.5 V / 1.8 V capable)
Programmable Technology — EEPROM (non-volatile)
In-System Programmable — Yes (IEEE Std. 1532 compliant)
Boundary-Scan Test — Yes (IEEE Std. 1149.1 JTAG)
Pin-Locking — Yes
Lead Finish — Lead-free (NiPdAu, AF suffix)
Configuration Memory Cycles — 100 erase/program cycles

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