EPM3064ATC44-4N vs EPM3064ATI44-10 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3064ATC44-4N sa pamamagitan ng Altera at EPM3064ATI44-10 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3064ATC44-4N EPM3064ATI44-10
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND NRND
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) —
Macro Cells 64 —
Logic Array Blocks 2 —
Number of I/Os 34 —
Dedicated Inputs 4 —
Usable Gates 1,250 —
Propagation Delay (tpd) 4.5 ns —
Maximum Counter Frequency 222.2 MHz 227.3 MHz
Supply Voltage (VCCINT) 3.3 V 3.3 V
I/O Supply Voltage (VCCIO) 2.5 V or 3.3 V —
Programmability EEPROM, in-system programmable (JTAG) —
JTAG Support IEEE Std. 1149.1 (boundary-scan) and IEEE Std. 1532 (ISP) —
Temperature na Operasyon 0C to +70C (commercial) -40C to +85C (Industrial)
Packhaging 44-pin TQFP TQFP-44 (10x10 mm, 0.8 mm pitch)
Uri ng Pagpapasok Surface Mount Surface Mount
Tindminan RoHS [DATA_NEEDED: rohs status] Non-Compliant (contains lead, per DigiChip listing)
Product Type — CPLD (Complex Programmable Logic Device)
Programmable Type — In-System Programmable (ISP), EEPROM-based
Number of Macrocells — 64
Number of Logic Array Blocks (LABs) — 4
Number of Usable Gates — 1,250
Number of User I/O Pins — 34
Pin-to-Pin Delay (tPD) — 10 ns
I/O Voltage Tolerance — 5.0 V tolerant (MultiVolt I/O)
JTAG Interface — IEEE Std. 1149.1 compliant
ISP Standard — IEEE Std. 1532
Lead Free Status — Contains Lead
Process Technology — CMOS, EEPROM
Programming Cycles — [DATA_NEEDED: typical program/erase endurance]

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