EPM3064ATC44-4N vs EPM3064ATI44-10N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3064ATC44-4N sa pamamagitan ng Altera at EPM3064ATI44-10N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3064ATC44-4N EPM3064ATI44-10N
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) —
Macro Cells 64 —
Logic Array Blocks 2 —
Number of I/Os 34 —
Dedicated Inputs 4 4
Usable Gates 1,250 1250
Propagation Delay (tpd) 4.5 ns —
Maximum Counter Frequency 222.2 MHz —
Supply Voltage (VCCINT) 3.3 V —
I/O Supply Voltage (VCCIO) 2.5 V or 3.3 V 3.3 V or 2.5 V (MultiVolt)
Programmability EEPROM, in-system programmable (JTAG) —
JTAG Support IEEE Std. 1149.1 (boundary-scan) and IEEE Std. 1532 (ISP) —
Temperature na Operasyon 0C to +70C (commercial) -40C to +85C (Industrial, "N" suffix)
Packhaging 44-pin TQFP 44-pin TQFP
Uri ng Pagpapasok Surface Mount Surface Mount
Tindminan RoHS [DATA_NEEDED: rohs status] Non-Compliant (per digchip datasheet excerpt)
Product Type — CPLD (Complex Programmable Logic Device)
Macrocells — 64
User I/Os — 34
Logic Blocks — 4
Pin-to-Pin Delay — 10 ns (-10 speed grade)
Maximum Frequency (fMAX) — 100 MHz
Programmable Type — In-System Programmable (EEPROM)
ISP Interface — IEEE Std. 1149.1 (JTAG)
ISP Standard Compliance — IEEE Std. 1532
Core Supply Voltage (VCCINT) — 3.3 V
Process Technology — CMOS EEPROM
Boundary-Scan Test — Built-in (JTAG)
Lead-Free Status — Contains Lead (per digchip datasheet excerpt)

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