EPM3064ATI100-10 vs EPM3064ATC100-4N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3064ATI100-10 sa pamamagitan ng Intel at EPM3064ATC100-4N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM3064ATI100-10 | EPM3064ATC100-4N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Number of Macrocells | 64 | — |
| Number of Logic Array Blocks (LABs) | 4 | — |
| Number of User I/Os | 66 | — |
| Usable Gates | 1,250 | 1,250 |
| Volte ng Pagbibigay | 3.3 V | — |
| Speed Grade | -10 (10 ns pin-to-pin) | — |
| Programmable Type | In-System Programmable (EEPROM) | — |
| Programming Interface | IEEE Std. 1149.1 JTAG | IEEE Std. 1149.1 JTAG (ISP) |
| Packhaging | 100-pin TQFP | 100-pin TQFP |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Operating Temperature Grade | Industrial | — |
| Lead Free Status | Contains Lead | — |
| Tindminan RoHS | Non-Compliant | [DATA_NEEDED: RoHS status] |
| Macro Cells | — | 64 |
| Logic Array Blocks | — | 2 |
| User I/O Pins | — | 66 |
| Pin-to-Pin Delay (tPD) | — | 4.5 ns |
| Counter Frequency | — | 222.2 MHz (max) |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 3.3 V or 2.5 V |
| ISP Standard | — | IEEE Std. 1532 |
| Temperature na Operasyon | — | 0C to +70C (commercial) |
| Process Technology | — | CMOS EEPROM |