EPM3064ATI44-10N vs EPM3064ATC44-10 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3064ATI44-10N sa pamamagitan ng Altera at EPM3064ATC44-10 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM3064ATI44-10N | EPM3064ATC44-10 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 3000A | MAX 3000A |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 64 | — |
| Usable Gates | 1250 | 1,250 |
| User I/Os | 34 | — |
| Dedicated Inputs | 4 | — |
| Logic Blocks | 4 | — |
| Pin-to-Pin Delay | 10 ns (-10 speed grade) | — |
| Maximum Frequency (fMAX) | 100 MHz | — |
| Programmable Type | In-System Programmable (EEPROM) | — |
| ISP Interface | IEEE Std. 1149.1 (JTAG) | — |
| ISP Standard Compliance | IEEE Std. 1532 | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V or 2.5 V (MultiVolt) | — |
| Temperature na Operasyon | -40C to +85C (Industrial, "N" suffix) | — |
| Packhaging | 44-pin TQFP | TQFP-44, 10 x 10 mm, 0.8 mm pitch |
| Process Technology | CMOS EEPROM | — |
| Boundary-Scan Test | Built-in (JTAG) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Lead-Free Status | Contains Lead (per digchip datasheet excerpt) | — |
| Tindminan RoHS | Non-Compliant (per digchip datasheet excerpt) | Non-compliant (legacy Altera, Pb-bearing) |
| Logic Elements / Macrocells | — | 64 macrocells |
| Number of Logic Blocks / LABs | — | 4 LABs |
| Propagation Delay (tPD) | — | 10 ns |
| Maximum Internal Frequency | — | 227.3 MHz (counter speed) |
| Programmable I/Os | — | 34 |
| Supply Voltage (VCCINT) | — | 3.0 V to 3.6 V (3.3 V typical) |
| I/O Bank Voltage (VCCIO) | — | MultiVolt 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Technology | — | CMOS EEPROM, 5 V tolerant I/O |
| In-System Programming | — | IEEE Std. 1532 (JTAG) |
| Boundary-Scan Support | — | IEEE 1149.1 (JTAG) |
| Hanay ng Temperature na Operasyon | — | 0C to +70C (commercial) |