EPM3064ATI44-10NAE vs EPM3064ATC44-10N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3064ATI44-10NAE sa pamamagitan ng Intel at EPM3064ATC44-10N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPM3064ATI44-10NAE - MAX 3000A CPLD, 64 Macro, 34 I/O, 10ns | Intel
EPM3064ATI44-10NAE ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EPM3064ATI44-10NAE | EPM3064ATC44-10N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | MAX 3000A | MAX 3000A |
| Device Family | EPM3064A | — |
| Macrocells | 64 | — |
| Usable Gates | 1250 | 1250 |
| User I/O Pins | 34 | 34 |
| Logic Elements (LABs) | 4 | — |
| Pin-to-Pin Delay (tPD) | 10 ns | 10 ns |
| Maximum Frequency (fMAX) | [DATA_NEEDED: maximum internal frequency MHz] | — |
| Supply Voltage VCCINT | 3.0 V to 3.6 V | — |
| I/O Supply Voltage VCCIO | 2.5 V / 3.3 V / 5.0 V (MultiVolt) | — |
| Temperature na Operasyon | -40 °C to +85 °C (industrial) | 0C to +70C (commercial) |
| Packhaging | 44-pin TQFP | TQFP-44 (10x10 mm) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Programmable Technology | CMOS EEPROM | — |
| In-System Programmable | Yes (JTAG, IEEE 1149.1) | — |
| Lead-Free / RoHS | Yes (AE suffix) | — |
| Katayuan ng Lifecycle | Active (MAX 3000A legacy family) | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 64 |
| Logic Array Blocks (LABs) | — | 4 |
| Maximum Counter Frequency | — | 192.3 MHz |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Standard | — | MultiVolt (mixed 1.5 V / 1.8 V / 2.5 V / 3.3 V) |
| Configuration Memory | — | EEPROM (non-volatile) |
| In-System Programming | — | IEEE Std. 1532 compliant |
| Boundary-Scan Test | — | IEEE Std. 1149.1 (JTAG) compliant |
| Tindminan RoHS | — | Compliant |
| Pin-Locking | — | Yes (across design iterations) |