EPM3064ATI44-4N vs EPM3064ALC44-4N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3064ATI44-4N sa pamamagitan ng Altera at EPM3064ALC44-4N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM3064ATI44-4N | EPM3064ALC44-4N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Huling Pagbili |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Logic Elements / Macrocells | 64 macrocells | 64 macrocells |
| Usable Gates | 1,250 gates | 1.25K |
| Number of Logic Array Blocks (LABs) | 4 LABs (16 macrocells each) | — |
| Maximum Operating Frequency | 222.2 MHz | 222.2 MHz |
| Pin-to-Pin Propagation Delay (tPD) | 4.5 ns (-4 speed grade) | — |
| Supply Voltage - Core (VCCINT) | 3.3 V | — |
| Supply Voltage - I/O (VCCIO) | 3.3 V or 2.5 V | — |
| User I/O Pins | 34 I/O | — |
| Packhaging | 44-pin TQFP | 44-pin PLCC (J-lead) |
| Temperature na Operasyon | -40C to +85C (industrial) | 0C to +70C (commercial) |
| Programming Interface | IEEE Std. 1149.1 JTAG, IEEE Std. 1532 ISP | IEEE Std 1149.1 JTAG |
| Configuration Memory | EEPROM (non-volatile) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS compliance status] |
| Logic Array Blocks (LABs) | — | 2 |
| Number of I/O Pins | — | 34 |
| Propagation Delay (tPD) | — | 4.5 ns |
| Supply Voltage - Core | — | 3.3 V |
| I/O Logic Level Support | — | 5.0 V / 3.3 V / 2.5 V (MultiVolt) |
| Program Memory Type | — | EEPROM (in-system programmable) |
| Hot Socketing | — | Supported |