EPM3128ATC144-5N vs EPM3128ATI144-5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3128ATC144-5N sa pamamagitan ng Altera at EPM3128ATI144-5N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM3128ATC144-5N | EPM3128ATI144-5N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | NRND |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD - Complex Programmable Logic Device | — |
| Logic Family | CMOS | — |
| Macrocells | 128 | — |
| Usable Gates | 2500 | — |
| User I/O | 96 | — |
| Pin-to-Pin Logic Delay | 5 ns | — |
| Counter Frequency | up to 227.3 MHz | — |
| Supply Voltage (Core) | 3.3 V | — |
| I/O Logic Levels Supported | 5.0 V / 3.3 V / 2.5 V (MultiVolt) | — |
| In-System Programmability | Yes (3.3-V via JTAG) | — |
| JTAG Boundary Scan | IEEE Std 1149.1 compliant | — |
| Packhaging | 144-pin TQFP (20x20 mm) | TQFP-144 (20x20 mm, 0.5 mm pitch) |
| Temperature na Operasyon | 0C to 70C (Commercial) | -40C to +85C (industrial) |
| Tindminan RoHS | Compliant (lead-free) | [DATA_NEEDED: RoHS status] |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Logic Gates | — | 2,500 gates |
| Macro Cells | — | 128 |
| User I/Os | — | 96 |
| Maximum Operating Frequency | — | 192.3 MHz |
| Pin-to-Pin Propagation Delay (tPD) | — | 5.0 ns |
| Supply Voltage (VCCINT) | — | 3.0 V to 3.6 V (3.3 V nominal) |
| I/O Standard | — | LVCMOS / LVTTL (5.0 V tolerant inputs) |
| Programming Interface | — | JTAG (IEEE 1149.1 BST) - in-system |
| Process Technology | — | 0.30 um CMOS EEPROM |
| Configuration Memory | — | Non-volatile on-chip EEPROM |
| Level ng MSL | — | 3 (168 hours) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |