EPM3128ATI10010N vs EPM3128ATI100-5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3128ATI10010N sa pamamagitan ng Altera at EPM3128ATI100-5N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPM3128ATI100-5N - MAX 3000A CPLD, 128 Macrocells, TQFP-100 | Intel / Altera
EPM3128ATI100-5N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EPM3128ATI10010N | EPM3128ATI100-5N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 128 | — |
| Logic Array Blocks (LABs) | 8 | 8 (16 macrocells per LAB) |
| Usable Gates | 2,500 | — |
| User I/Os | 80 | — |
| Bilang ng Pins | 100 | — |
| Packhaging | 100-pin TQFP | 100-pin TQFP |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Internal Frequency | 98 MHz | — |
| Core Supply Voltage | 3.0 V to 3.6 V | — |
| I/O Bank Voltage | 1.8 V / 2.5 V / 3.3 V | — |
| Temperature na Operasyon | 0 C to +70 C (commercial) | -40C to +85C (Industrial) |
| Process Technology | CMOS EEPROM | — |
| Programming Interface | JTAG (IEEE 1149.1) ISP | — |
| PCI Compliance | Yes (speed grades -5/-6/-7/-10) | — |
| Tindminan RoHS | unknown | Compliant (lead-free TQFP package) |
| Macrocells | — | 128 |
| User I/O Pins | — | 80 |
| Pin-to-Pin Delay (tPD) | — | 5.0 ns |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Standard | — | 3.3 V LVCMOS / LVTTL, 5.0 V tolerant inputs |
| Programming Method | — | In-System Programmable via IEEE Std. 1532 (JTAG) |
| Configuration Memory | — | Non-volatile EEPROM |
| JTAG Support | — | IEEE 1149.1 boundary scan |