EPM3256AFC256-10 vs EPM3512AFC256-18 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3256AFC256-10 sa pamamagitan ng Altera at EPM3512AFC256-18 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3256AFC256-10 EPM3512AFC256-18
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Huling Pagbili Obsolete
Family MAX 3000A MAX 3000A
Logic Family CMOS (EEPROM-based) —
Device Type CPLD (Complex Programmable Logic Device) —
Macro Cells 256 —
Usable Gates 5,000 —
Logic Array Blocks (LABs) 16 (16 macrocells each) 16
Maximum User I/Os 161 —
Propagation Delay (tPD) 10 ns —
Internal Counter Frequency (fCNT) 95.2 MHz —
Supply Voltage (VCCINT) 3.3 V —
I/O Voltage Tolerance 5.0 V tolerant —
In-System Programmability Yes (3.3 V ISP via JTAG IEEE 1149.1) —
Temperature na Operasyon 0°C to +70°C (Commercial) [DATA_NEEDED: industrial/commercial grade]
Packhaging 256-ball FBGA (Fine-Line BGA) 256-ball FineLine BGA (FCBGA)
Pitch [DATA_NEEDED: BGA ball pitch] —
Uri ng Pagpapasok Surface Mount Surface Mount
Tindminan RoHS [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: not specified in retrieved data]
Macrocells — 512
Maximum User I/O Pins — 212
Pin-to-Pin Delay (tPD1) — 18 ns
Global Clock Networks — 4
VCCINT (Core Supply) — 3.0 V to 3.6 V (3.3 V typical)
VCCIO (I/O Supply) — 2.5 V or 3.3 V (MultiVolt)
Programming Technology — EEPROM (non-volatile)
In-System Programming — IEEE Std. 1532 / JTAG (IEEE Std. 1149.1)
Ball Pitch — 1.0 mm

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