EPM3256AFC256-10N vs EPM3256AFI256-10 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3256AFC256-10N sa pamamagitan ng Altera at EPM3256AFI256-10 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPM3256AFI256-10 - 256-Macrocell CPLD, 10ns, FBGA-256 | Intel
EPM3256AFI256-10 ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EPM3256AFC256-10N | EPM3256AFI256-10 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Huling Pagbili |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 5,000 gates | — |
| Macrocells | 256 | 256 |
| Maximum User I/O | 161 | — |
| Pin-to-Pin Logic Delay | 10 ns | — |
| Maximum Counter Frequency | 227.3 MHz | — |
| Core Voltage | 3.3 V | — |
| I/O Logic Level Compatibility | 5.0 V / 3.3 V / 2.5 V (MultiVolt) | — |
| Programmability | EEPROM, in-system programmable (ISP) | In-System Programmable (ISP) via IEEE 1149.1 JTAG |
| JTAG Interface | IEEE 1532 / JTAG (TDI, TDO, TMS, TCK) | — |
| Packhaging | 256-pin FineLine BGA | — |
| Logic Family | CMOS | — |
| PCI Compliance | PCI Local Bus Specification Rev 2.2 (at -10 grade) | — |
| Temperature na Operasyon | 0 C to 70 C (commercial) | -40C to +85C (Industrial) |
| User I/Os | — | 161 |
| Logic Elements / LABs | — | 16 Logic Elements per LAB |
| Propagation Delay (tPD) | — | 10 ns |
| Supply Voltage - Core | — | 3.3 V |
| I/O Voltage Support | — | 5.0 V / 3.3 V / 2.5 V (MultiVolt I/O) |
| Process Technology | — | CMOS EEPROM |
| Package Type | — | FBGA-256 (FineLine BGA) |
| Uri ng Pagpapasok | — | Surface Mount (BGA) |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS compliance status] |
| Speed Grade | — | -10 (10 ns pin-to-pin) |