EPM3256ATC144-10N vs EPM3256ATI144-10 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3256ATC144-10N sa pamamagitan ng Altera at EPM3256ATI144-10 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM3256ATC144-10N - 256-Macro CPLD, 10ns, 144-TQFP | Altera
EPM3256ATC144-10N ⚠ Huling Pagbili
Pagsanggunian na paghahambing
| Parametro | EPM3256ATC144-10N | EPM3256ATI144-10 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Series | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macro Cells | 256 | — |
| Usable Gates | 5,000 (up to 10,000 usable in family) | — |
| Number of I/Os | 116 | — |
| Number of Logic Elements / Blocks | 16 LABs | 16 LABs (Logic Array Blocks) |
| Supply Voltage (VCCINT) | 3.3 V | 3.0 V to 3.6 V (3.3 V nominal) |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Counter Frequency | 227.3 MHz | — |
| Global Clocks | 3 | — |
| Global Clear / OE | Yes (1 global clear, 1 global OE) | — |
| Program Memory Type | EEPROM (non-volatile, in-system programmable) | — |
| JTAG Support | IEEE Std. 1149.1 with pin-locking | — |
| ISP Compliance | IEEE Std. 1532 | — |
| Boundary-Scan Test (BST) | Built-in, IEEE 1149.1 compliant | — |
| Packhaging | 144-LQFP (TQFP, ATC suffix) | 144-pin TQFP (20x20 mm) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | 0C to +70C (commercial) [DATA_NEEDED: exact operating-temp grade letter for -10N suffix] | -40°C to +85°C (industrial) |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance - not explicitly confirmed in verified data] | — |
| Lead-Free / Halogen-Free | [DATA_NEEDED: not explicitly confirmed in verified data] | — |
| Programmable Type | — | In-System Programmable (ISP), EEPROM-based |
| Number of Macrocells | — | 256 |
| Number of Gates | — | 5,000 typical usable gates |
| Number of User I/O | — | 116 |
| Propagation Delay (tpd max) | — | 10 ns |
| Maximum Frequency (fmax) | — | 95.2 MHz |
| I/O Voltage Support | — | MultiVolt: 1.8 V / 2.5 V / 3.3 V / 5.0 V mixed |
| Logic Family | — | CMOS, EEPROM-based |
| Programming Interface | — | JTAG (IEEE 1149.1) and IEEE Std. 1532 ISP |
| Compliance | — | IEEE Std. 1532 ISP, PCI-compatible I/O |
| Katayuan ng Lifecycle | — | Obsolete (per HighqualityPCB listing) |