EPM3256ATC44-7 vs EPM3064ATC44-10 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3256ATC44-7 sa pamamagitan ng Altera at EPM3064ATC44-10 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3256ATC44-7 EPM3064ATC44-10
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) —
Macro Cells 256 —
Logic Array Blocks (LABs) 16 —
Packhaging TQFP-44 TQFP-44, 10 x 10 mm, 0.8 mm pitch
Pin-to-Pin Propagation Delay (tPD) 7.5 ns —
Maximum Internal Frequency (fCNT) 175.4 MHz (family rating) —
User I/O (this package) [DATA_NEEDED: I/O count for 44-pin TQFP variant] —
Supply Voltage (VCCINT) 3.3 V 3.0 V to 3.6 V (3.3 V typical)
I/O Voltage (VCCIO) 3.3 V (5.0 V-tolerant input) —
Process Technology 0.30 µm CMOS EEPROM —
In-System Programmability 3.3 V ISP via IEEE 1149.1 JTAG —
Operating Temperature (commercial) 0 C to +70 C —
Non-volatile Configuration Yes (EEPROM) —
Tindminan RoHS Compliant (Lead-free) Non-compliant (legacy Altera, Pb-bearing)
Logic Family CMOS —
Logic Elements / Macrocells — 64 macrocells
Usable Gates — 1,250
Number of Logic Blocks / LABs — 4 LABs
Propagation Delay (tPD) — 10 ns
Maximum Internal Frequency — 227.3 MHz (counter speed)
Programmable I/Os — 34
I/O Bank Voltage (VCCIO) — MultiVolt 1.5 V / 1.8 V / 2.5 V / 3.3 V
Technology — CMOS EEPROM, 5 V tolerant I/O
In-System Programming — IEEE Std. 1532 (JTAG)
Boundary-Scan Support — IEEE 1149.1 (JTAG)
Uri ng Pagpapasok — Surface Mount
Hanay ng Temperature na Operasyon — 0C to +70C (commercial)

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