EPM3512AFC256-19 vs EPM3512AFC-7N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3512AFC256-19 sa pamamagitan ng Altera at EPM3512AFC-7N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPM3512AFC-7N - 512-Macrocell MAX 3000A CPLD, 7.5ns, BGA-256 | Intel (Altera)
EPM3512AFC-7N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EPM3512AFC256-19 | EPM3512AFC-7N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Aktibo |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 512 | 512 |
| Usable Gates | 10000 | — |
| Logic Array Blocks (LABs) | 16 | 16 |
| Maximum Operating Frequency | 80 MHz | — |
| Pin-to-Pin Delay (tPD) | 7.5 ns | — |
| Speed Grade | -19 | — |
| User I/O Pins | 208 | — |
| Packhaging | 256-ball FineLine BGA (FC) | BGA-256 (FineLine BGA) |
| Supply Voltage VCCINT | 3.3 V | — |
| I/O Supply Voltage VCCIO | 2.5 V or 3.3 V (5.0 V tolerant inputs) | — |
| Programming Interface | JTAG (IEEE 1149.1) / ISP (IEEE 1532) | JTAG (4-wire TCK/TMS/TDI/TDO) |
| Process Technology | 0.30 µm CMOS EEPROM | — |
| Temperature na Operasyon | -40C to +85C (industrial) | 0 C to +70 C (commercial) |
| Non-volatile Configuration | Yes (EEPROM-based) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (BGA) |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| User I/Os | — | 208 |
| Dedicated Inputs | — | 16 |
| Propagation Delay (tPD) | — | 7.5 ns (speed grade -7) |
| Logic Family | — | CMOS, EEPROM-based |
| Core Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | MultiVolt: 1.8 V / 2.5 V / 3.3 V / 5.0 V tolerant |
| In-System Programmability | — | Yes - IEEE Std. 1532 / JTAG (IEEE 1149.1) |