EPM3512AFC256-2 vs EPM3512AFC256-3N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3512AFC256-2 sa pamamagitan ng Altera at EPM3512AFC256-3N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM3512AFC256-2 | EPM3512AFC256-3N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Aktibo |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | 512 |
| Logic Array Blocks (LABs) | 16 | 16 |
| Maximum User I/O Pins | 212 | — |
| Propagation Delay (tPD, -2 grade) | [DATA_NEEDED: tPD ns] | — |
| Maximum Operating Frequency | [DATA_NEEDED: fMAX MHz] | 116.3 MHz |
| Core Supply Voltage | 3.3 V | — |
| I/O Output Drive Voltage | 2.5 V or 3.3 V (MultiVolt) | — |
| Input Tolerance | 2.5 V, 3.3 V, 5.0 V tolerant | — |
| Packhaging | BGA-256 (FineLine BGA) | 256-ball FineLine BGA (FC-256) |
| Ball Pitch | 1.0 mm | — |
| Programming Interface | JTAG (IEEE Std 1149.1) / ByteBlaster | JTAG (IEEE 1149.1) / IEEE Std. 1532 ISP |
| Process Technology | 0.30 um CMOS EEPROM | — |
| Temperature na Operasyon | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature grade] |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Speed Grade | -2 | -3 (slowest in family) |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 10,000 |
| Pin-to-Pin Delay (tPD) | — | 3.5 ns (speed grade -3) |
| Core Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Supply Voltage (VCCIO) | — | 2.5 V / 3.3 V / 5.0 V (MultiVolt) |
| Uri ng Pagpapasok | — | Surface Mount |
| Configuration Memory | — | Non-volatile EEPROM |