EPM3512AFC256-2 vs EPM3512AFC256-7N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3512AFC256-2 sa pamamagitan ng Altera at EPM3512AFC256-7N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3512AFC256-2 EPM3512AFC256-7N
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 3000A MAX 3000A
Macrocells 512 512
Logic Array Blocks (LABs) 16 —
Maximum User I/O Pins 212 —
Propagation Delay (tPD, -2 grade) [DATA_NEEDED: tPD ns] —
Maximum Operating Frequency [DATA_NEEDED: fMAX MHz] —
Core Supply Voltage 3.3 V —
I/O Output Drive Voltage 2.5 V or 3.3 V (MultiVolt) —
Input Tolerance 2.5 V, 3.3 V, 5.0 V tolerant —
Packhaging BGA-256 (FineLine BGA) 256-pin FineLine BGA (FBGA-256), 1.0 mm pitch
Ball Pitch 1.0 mm —
Programming Interface JTAG (IEEE Std 1149.1) / ByteBlaster JTAG (IEEE 1149.1)
Process Technology 0.30 um CMOS EEPROM CMOS EEPROM, 0.30 um
Temperature na Operasyon 0C to +70C (commercial) 0 C to 70 C (commercial)
Tindminan RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Speed Grade -2 —
Product Type — CPLD (Complex Programmable Logic Device)
Usable Gates — 10,000
User I/Os — 208
Logic Blocks — 16 (32 macrocells each)
Propagation Delay (tPD) — 7.5 ns
Maximum Internal Frequency (fMAX) — 116.3 MHz
Core Supply Voltage (VCCINT) — 3.3 V
I/O Supply Voltage (VCCIO) — 3.3 V or 2.5 V
5V Tolerant I/O — Yes
In-System Programmability — IEEE Std. 1532 compliant
Uri ng Pagpapasok — Surface Mount

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