EPM3512AFC256-22 vs EPM3256AFC256-10 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3512AFC256-22 sa pamamagitan ng Intel at EPM3256AFC256-10 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3512AFC256-22 EPM3256AFC256-10
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Huling Pagbili
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 512 —
Logic Array Blocks (LABs) 16 16 (16 macrocells each)
Maximum User I/O Pins 208 (typical for FC256 package) —
Speed Grade -22 (tPD ~22 ns) —
Propagation Delay (tPD) 22 ns 10 ns
Supply Voltage VCCINT 3.3 V —
I/O Standards Supported 2.5 V, 3.3 V, 5.0 V (VCCIO selectable) —
In-System Programming IEEE Std. 1532-compliant ISP via JTAG —
Configuration Memory On-chip EEPROM (non-volatile) —
Packhaging FC-256 (FineLine BGA, 256 balls, 1.0 mm pitch) 256-ball FBGA (Fine-Line BGA)
Uri ng Pagpapasok Surface Mount (BGA) Surface Mount
Temperature na Operasyon [DATA_NEEDED: operating temperature grade] 0°C to +70°C (Commercial)
Tindminan RoHS [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS compliance status]
Logic Family — CMOS (EEPROM-based)
Macro Cells — 256
Usable Gates — 5,000
Maximum User I/Os — 161
Internal Counter Frequency (fCNT) — 95.2 MHz
Supply Voltage (VCCINT) — 3.3 V
I/O Voltage Tolerance — 5.0 V tolerant
In-System Programmability — Yes (3.3 V ISP via JTAG IEEE 1149.1)
Pitch — [DATA_NEEDED: BGA ball pitch]

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