EPM3512AQC210-10 vs EPM3512AQC208-10N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3512AQC210-10 sa pamamagitan ng Altera at EPM3512AQC208-10N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3512AQC210-10 EPM3512AQC208-10N
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Logic Macrocells 512 —
Logic Array Blocks (LABs) 16 (32 macrocells each) 16
Maximum User I/O Pins 172 —
Speed Grade -10 (10 ns tPD) -10
Pin-to-Pin Propagation Delay (tPD1, max) 10 ns —
Maximum Operating Frequency (fCNT) 125 MHz —
Supply Voltage - Core (VCCINT) 3.3 V —
Supply Voltage - I/O (VCCIO) 3.3 V or 2.5 V —
Input Voltage Tolerance 5.0 V tolerant —
Programmable Technology EEPROM (in-system programmable) —
Programming Interface JTAG (IEEE 1149.1) / ISP —
Packhaging PQFP-210 208-pin PQFP (Plastic Quad Flat Pack)
Temperature na Operasyon 0C to +70C (commercial) 0 C to 70 C (commercial)
Uri ng Pagpapasok Surface Mount —
Tindminan RoHS [DATA_NEEDED: rohs_compliance_status] [DATA_NEEDED: RoHS status not in verified web data]
Macrocells — 512
Usable Gates — Up to 10,000
User I/Os — 172
Volte ng Pagbibigay — 3.3 V
Pin-to-Pin Delay — 4.5 ns (-10 speed grade)
Maximum Internal Frequency — 227.3 MHz
Process Technology — CMOS EEPROM
In-System Programming — IEEE Std. 1149.1 JTAG, IEEE Std. 1532
Boundary-Scan Test (BST) — Built-in, IEEE 1149.1 compliant
I/O Standards — MultiVolt (1.8V / 2.5V / 3.3V)

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