EPM3512ATC144-10N vs EPM3512ATC144-10 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3512ATC144-10N sa pamamagitan ng Intel at EPM3512ATC144-10 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPM3512ATC144-10N - MAX 3000A CPLD, 512 Macrocells, 144-TQFP | Intel
EPM3512ATC144-10N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EPM3512ATC144-10N | EPM3512ATC144-10 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | NRND |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 512 | 512 |
| Logic Array Blocks (LABs) | 16 | 16 (32 macrocells each) |
| Usable Gates | 10000 | 10,000 |
| Maximum User I/O | 212 | 212 (212 device-max; 114 in 144-pin TQFP) |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Frequency (fMAX) | [DATA_NEEDED: fMAX in MHz] | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V / 5 V (MultiVolt) | — |
| Configuration Memory | Non-volatile EEPROM | — |
| Programming Interface | JTAG (IEEE 1149.1), in-system programmable | JTAG (IEEE Std. 1149.1) ISP |
| Packhaging | 144-pin TQFP (TC144) | TQFP-144 (14x14 mm) |
| Temperature na Operasyon | 0C to +70C (commercial, N suffix) | -40C to +85C (industrial) |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance from datasheet] | Compliant (lead-free) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Pin-to-Pin Logic Delay (tPD) | — | 10 ns |
| Setup Time (tSU) | — | 7.0 ns |
| Clock-to-Output (tCO) | — | 6.5 ns |
| Maximum Operating Frequency | — | 116.0 MHz |
| Supply Voltage (Core) | — | 3.3 V |
| MultiVolt I/O Voltages | — | 2.5 V / 3.3 V / 5.0 V |