EPM5016LC-17 vs EPM5016DC-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5016LC-17 sa pamamagitan ng Altera at EPM5016DC-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5016LC-17 | EPM5016DC-20 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 5000 EPLD | MAX 5000 |
| Technology | CMOS, UV-erasable | — |
| Macrocells | 16 | 16 |
| Product Terms | 160 | 160 |
| Dedicated Inputs | 7 | 7 |
| I/O Pins | 8 | 8 |
| Total Input Pins | 16 | — |
| Outputs | 8 | — |
| External Clock Inputs | 1 | — |
| Propagation Delay (tPD) | 17 ns | 20 ns |
| Architecture | PAL-type with Programmable Interconnect Array (PIA) | PAL-type macrocell with Programmable Interconnect Array (PIA) |
| Packhaging | Windowed Ceramic DIP (LC) | — |
| Volte ng Pagbibigay | [DATA_NEEDED: VCC range] | — |
| Temperature na Operasyon | [DATA_NEEDED: temperature grade] | [DATA_NEEDED: operating temperature range] |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance] |
| Logic Compatibility | TTL/CMOS | — |
| Device Type | — | EPLD (UV-Erasable Programmable Logic Device) |
| Maksimum na Taktiko ng Oras | — | 62.5 MHz |
| Maximum Supply Voltage | — | 5.25 V |
| Nominal Supply Voltage | — | 5.0 V |
| Process Technology | — | CMOS, UV-erasable |
| Package Type | — | 20-pin Ceramic DIP (Cerdip) with UV window |
| Package Suffix Code | — | DC = Ceramic DIP, Commercial |
| Speed Grade | — | -20 = 20 ns tPD |
| Programming Method | — | UV erase + EPROM-style programming via Altera programming hardware |